Comparator

ABSTRACT

A comparator which sets the comparison level depending on the number of transistors used easily ascertains the relative accuracy of the load resistors, is suitable for integration and improves the relative accuracy of input DC biases.

BACKGROUND OF THE INVENTION

This invention relates to a comparator.

A conventional comparator generally has a structure such as that shownin FIG. 3 in which a transistor T₃ is connected in series with aresistor R₃, a transistor T₄ is connected in series with a resistor R₄,the junction of transistor T₃ and resistor R₃ and the junction oftransistor T₄ and resistor R₄ are connected to inputs of a differentialamplifier A which produces an output corresponding to the differencebetween the signals supplied to the bases of transistors T₃ and T₄.

In this arrangement, setting a comparison level is performed by changinga reference potential in the case of a single input while it isperformed by changing resistors R₃, R₄ in the case of a differentialinput.

The setting of the comparison level in the case of the differentialinput will now be described. If the difference between the inputs to thebases of transistors T₃ and T₄ is represented by Vi, and a change in thecurrent is represented by i, currents (I+i), (-i) flow throughtransistors T₃ and T₄, respectively, and the respective collectorpotentials V_(t1c), V_(t2c) are given by

    V.sub.t1c =V.sub.cc -R.sub.3 (I+i)

    V.sub.t2c =V.sub.cc -R.sub.4 (i-i)

Since V_(t1c) =V_(t2c), the comparator starts to operate when thecomparison level is

    i=I(R.sub.4 -R.sub.3)/(R.sub.3 +R.sub.4)

It can be seen from this equation that when, for example, R₃ =R₄, thecomparator operates with i=0, while when R₄ =2 R₃, the comparatoroperates with i=I/3. Namely, when R₄ =2R₃, the comparator operates withapplication of an operating input voltage v₁ thereto such that a currenti=I/3 flows therethrough.

A drawback in the above circuit arrangement is that when the comparisonlevel is set with a reference voltage, the reference voltage and aninput potential to be compared must be of high accuracy.

In the case of a differential input, as described above, the comparisonlevel is determined by (R₄ -R₃)/(R₃ +R₄), so that disadvantageously therelative accuracy of the resistors is required. Especially, when theresistances of resistors R₃ and R₄ are different, integration isdifficult.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit diagram showing one embodiment of thisinvention.

FIG. 2 is an electric circuit diagram showing another embodiment.

FIG. 3 is an electric circuit diagram showing a conventional comparator.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, m(m=1, 2 . . . ) transistors T₁ ˜T₁ are connected in paralleland an input terminal a is connected to the respective bases of thetransistors. A load resistor R₁ is connected in series with thatcircuit. Also, n(n=1, 2 . . . but n≠m) transistors T₂ ˜T₂ are connectedin parallel and an input terminal b is connected to the respective basesof the transistors. A load resistor R₂ is also connected in series withthis circuit. The resistors R₁ and R₂ have the same resistance so as tofacilitate integration. The junction of resistor R₁ and transistorsT₁˜T₁ and the junction of resistor R₂ and transistors T₂ ˜T₂ areconnected to input terminals of a differential amplifier circuit A.

When a voltage v_(i) is applied across input terminals a, b, assume thata change current i flows through each transistor and that a bias current(m+n)I flows. A current (I+i₁) flows through each transistor T₁ while acurrent (I-i₂) flows through each transistor T₂. Since

    m(I+i.sub.1)+n(I-i.sub.2)=(m+n)I

    i.sub.2 =(m/n)i.sub.1

If collector voltages of transistors T₁ and T₂ are shown by V_(cm),V_(cn),

    V.sub.cm =V.sub.cc -R m(I+i.sub.1)

    V.sub.cn =V.sub.cc -R n(I-(m/n)i.sub.1)

Since V_(cm) =V_(cn), the comparison level is given by

    i.sub.1 =(n-m)I/2m

As just described, the comparison level is set by the number oftransistors T₁ and T₂. For example, when n=2, then comparison isperformed with m=1, and i₁ =I/2, and i₂ =I/4.

According to the above arrangement, the load resistors R₁ and R₂ can bearranged to have the same value to set the comparison level. Therefore,the relative accuracy of the load resistors is easy to obtain and thestructure is suitable for integration.

Now another embodiment will be described.

In FIG. 2, a first circuit includes m(m=1, 2 . . . ) transistors T₁ ˜T₁connected in parallel with each other with an input terminal a beingconnected to the respective bases of the transistors. A first loadresistor R₁ is connected in series with this circuit. A second circuitincludes n(n=1, 2 . . . , with n≠m) transistors T₂ with an inputterminal b being connected to the respective bases of the transistors. Asecond load resistor R₂ is connected in series with this circuit. Theresistors R₁ and R₂ have the same resistance so as to render integrationeasy. The junction of resistor R₁ and transistor T₁ and the junction ofresistor R₂ and transistor T₂ are connected to input terminals of adifferential amplifier circuit A. In addition to the above circuitstructure, (m-n) transistors T₃ with an input terminal b being connectedto the respective bases of the transistors are connected in parallelwith resistor R₂ and the second circuit.

When voltage v_(i) is applied across input terminals a and b, a current(I-i₁) flows through each transistor T₁ and a current (I+i₂) flowsthrough each of transistors T₂ and T₃ where i₁ and i₂ are changecurrents flowing through transistors T₁ and T₂, respectively, 2mI is thebias current. The following relationship holds from the quality of theoperational amplifier circuit

    m(I-i.sub.1)+n(I+i.sub.2)+(m-n)(I+i.sub.2)

    =2mI

Therefore, i₂ =i₁. If collector voltages of transistors T₁ and T₂ areshown by V_(cm), V_(cn), respectively, then

    V.sub.cm =V.sub.cc =R m(I-i.sub.1)

    V.sub.cn =V.sub.cc -R n(I+i.sub.1)

Since V_(cm) =V_(cn), the comparison level is given by

    i.sub.1 =(m-n)I/(m+n)

In this embodiment, the comparison level is set depending on the numberof transistors T₁, T₂ and T₃. For example, when m=2, n=1, the comparisonis performed with i₁ =I/3.

According to the above structure, the load resistors R₁ and R₂ can havethe same value and the comparison level can be set, so that the relativeaccuracy of the load resistors is easy to obtain, and the structure issuitable for integration. In addition, the input DC levels can have thesame voltage to determine the comparison level, so that the relativeaccuracy of input DC biases is easy to obtain.

According to this invention, the comparison level can be set dependingon the number of transistors used, so that the load resistors can havethe same value, the relative accuracy of resistors is easy to obtain andthe structure is suitable for integration. Since the input DC biases canhave the same voltage, the relative accuracy of biases is improved. Inaddition, quantities (absolute values) of changes in the collectorcurrents to the input voltages, and bias currents in the respectivetransistors are the same, so that setting the respective comparisonlevels is easy.

We claim:
 1. A comparator comprising:a first circuit including m(m=1,
 2. . . ) transistors connected in parallel for receiving a first inputsignal at each respective base of the transistors; a second circuitincluding n(n=1, 2 . . . where n≠m) transistors connected in parallelfor receiving a second input signal at each respective base of thetransistors; a first load resistor connected in series with the firstcircuit, and a second load resistor having the same resistance as thefirst load resistor and connected in series with the second circuit;said first circuit and said first load resistor constituting a firstseries-connected circuit, and said second circuit and said second loadresistor consituting a second series-connected circuit, said firstseries-connected circuit and said second series-connected circuit eachbeing connected in parallel with a common power source; and adifferential amplifier having input terminals respectively connected toa junction of the first load resistor and the first circuit and ajunction of the second load resistor and the second circuit.
 2. Thecomparator of claim 1; wherein each of said transistors of said firstcircuit is of the same type connected with the same orientation.
 3. Thecomparator of claim 1; wherein each of said transistors of said secondcircuit is of the same type connected with the same orientation.
 4. Thecomparator of claim 1; wherein each of said transistors of said firstand second circuits is of the same type connected with the sameorientation.
 5. The comparator of claim 1; wherein each transistor isconnected to said differential amplifier.
 6. The comparator of claim 1;wherein each transistor of said first circuit is connected to a firstterminal of said differential amplifier and each transistor of saidsecond circuit is connected to a second terminal of said differentialamplifier.
 7. The comparator of claim 6; wherein the collectors of eachtransistor of said first circuit are connected to said first terminal.8. The comparator of claim 6; wherein the collectors of each transistorof said second circuit are connected to said second terminal.
 9. Acomparator comprising:a first circuit including m(m=2, 3 . . . )transistors connected in parallel for receiving a first input signal ateach respective base of the transistors; a second circuit includingn(n=1, 2 . . . where n<m) transistors connected in parallel forreceiving a second input signal at each respective base of thetransistors; a third circuit including (m-n) transistors connected inparallel and receiving the second input signal at each respective baseof the transistors; a first load resistor through which the firstcircuit is connected to a power source, and a second load resistorhaving the same resistance as the first load resistor and through whichthe second circuit is connected to the power source; said third circuitconnected in parallel with a series-connected circuit including thesecond load resistor and the second circuit; and a differentialamplifier having input terminals respectively connected to a junction ofthe first load resistor and the first circuit and a junction of thesecond load resistor and the second circuit.
 10. The comparator of claim9; wherein each of said transistors of said first circuit is of the sametype connected with the same orientation.
 11. The comparator of claim 9;wherein each of said transistors of said second circuit is of the sametype connected with the same orientation.
 12. The comparator of claim 9;wherein each of said transistors of said first and second circuits is ofthe same type connected with the same orientation.
 13. The comparator ofclaim 9; wherein each transistor is connected to said differentialamplifier.
 14. The comparator of claim 9; wherein each transistor ofsaid first circuit is connected to a first terminal of said differentialamplifier and each transistor of said second circuit is connected to asecond terminal of said differential amplifier.
 15. The comparator ofclaim 9; wherein the collectors of each transistor of said first circuitare connected to said first terminal.
 16. The comparator of claim 9;wherein the collectors of each transistor of said second circuit areconnected to said second terminal.